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How to define parameters in SystemC?

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richa.verma

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How can parameters(generics in VHDL) be included in SystemC? Right now I am trying to convert a code written in VHDL to SystemC. The VHDL code has some generics(parameters). How can I convert them to SystemC code?
 

Hello Maulin

Consider an example of bus. The bus is such that its width can be varied i,e., parametrized.

entity xyz is
GENERIC(
P_BUS_WIDTH : NATURAL : 8; --! default bus width is 8
);
PORT(
a : IN std_logic_vector(P_BUS_WIDTH downto 0);
b : OUT std_logic_vector(P_BUS_WIDTH downto 0);
);
architecture abc of xyz is
begin
..
b<= a;
..
end abc

In the above example vector length of both a and b can be varied by varying the the value of P_BUS_WIDTH.
I would like to know how can I use "GENERIC" variables(in this example it is P_BUS_WIDTH) of VHDL in systemc? I hope now my question is clear!

- - - Updated - - -

1 more question. How can "GENERATE" statements of VHDL be used in systemc?
 

richa.verma said:
Hello Maulin

Consider an example of bus. The bus is such that its width can be varied i,e., parametrized.

entity xyz is
GENERIC(
P_BUS_WIDTH : NATURAL : 8; --! default bus width is 8
);
PORT(
a : IN std_logic_vector(P_BUS_WIDTH downto 0);
b : OUT std_logic_vector(P_BUS_WIDTH downto 0);
);
architecture abc of xyz is
begin
..
b<= a;
..
end abc

In the above example vector length of both a and b can be varied by varying the the value of P_BUS_WIDTH.
I would like to know how can I use "GENERIC" variables(in this example it is P_BUS_WIDTH) of VHDL in systemc? I hope now my question is clear!

- - - Updated - - -

1 more question. How can "GENERATE" statements of VHDL be used in systemc?
Click to expand...

I think U can define it like:
1) int P_BUS_WIDTH = 8; (SystemC is supported to C & CPP).

OR u can also do like
sc_int<4> a;
a = 8;
 
Last edited:

Thanks for your suggestion. What about "GENERATE" statements of VHDL?
 

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