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question about simulation of cap bank glitch

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danda821

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I want to simulate capacitor bank glitch. This is a 8bit binary cap bank. I can use AC or SP simulation find the total cap value vs. code. How can I run some transient simulation and find cap vs. time (code changes with time)? I want to see glitch size when code changes in real time.

Thanks.
 

Sounds like you missed to tell the context of your question...
But may be I'm wrong and many edaboard immediately guess what you're talking about.
 

Or how to find capacitor value in transient simulation? Thanks.

FvM said:
Sounds like you missed to tell the context of your question...
But may be I'm wrong and many edaboard immediately guess what you're talking about.
Click to expand...
 

danda821 said:
I want to simulate capacitor bank glitch. This is a 8bit binary cap bank. I can use AC or SP simulation find the total cap value vs. code. How can I run some transient simulation and find cap vs. time (code changes with time)? I want to see glitch size when code changes in real time.

Thanks.
Click to expand...

I did not quite understand why transient simulation should be a problem , you can create a clock source in spice , you can then either instantiate a counter model or construct a simple counter from FF's , You can then connect counter outputs to ideal switches / Mos switches as your wish . I do agree with the FvM that the context is not quite clear.
 

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