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How to work with VHDL library?

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mangohaha

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I am doing a project, must only use nand gate.
Here is my trouble:I designed with behavior description then get the technology schematic. The resut is, the xilinx implements it with and gates.
Here is my method: I made a package, with only nand gate, So the xilinx can only implement it with nands.
like this:
Code:
library ieee;
use IEEE.std_logic_1164.all;
Use work.my_components.all;
But, I still have to use the IEEE.std_logic_1164.all ...So still, xilinx implements using and gates.
Can I find the IEEE.std_logic_1164.all and delete the and gate? Or is there any other solutions?
Thanks....
 

The technology schematic hasn't to do with VHDL libraries. It's a visualization of the synthesized gate level net lists. It's not implemented with any kind of standard logic gates rather than programmable logic elements based on look-up-tables, called CLB in Xilinx FPGAs.

Unless your homework specifies a special synthesis procedure, it should be O.K. with using NAND gates for the structural description. Although there are some means to control the synthesis, it doesn't make sense for a basic FPGA exercise, I think.
 

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