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conversion of " and not " with verilog

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taoshen

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in a vhdl file, there are the two following expression:

===========================

variable tt : std_logic_vector(7 downto 0);
...
tt := (others => '-' );

if ( exp1 and not exp2 ）

===========================

how to express the same meaning of "-" and " and not " with VerilogHDL.
 

well im not sure what exactically "-" is.. my guess would be say 8'bxxxx_xxxx;..

as for the and not..

if ((expr1) & ~(expr2))

jelydonut
 

Thank jelydonut for kind help. : )

excuse me,thesr is another puzzling question about is_x

==========================
pc : std_logic_vector(31 downto 0);

...

if not is_x(pc) then
...
==========================
The "is_x" means that each bit of the vector are "x" or some of the vector are "x" .
I try to find the definition of "is_x". but fail.
are the "is_x" a user-defined function or constant ?
 

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