Current mirror topology

Hey all,

I'm currently looking at various current mirror topologies. Take a look at attached picture. The first ("normal" current mirror) and third (low voltage cascode mirror) are described in Razavi's book. The second I have stumbled upon looking at other designs. Curious about there performance, I simulated all three topologies: M1/M3 rather large W/L ratio and M2/M4 rather low W/L ratio. The output current of the second topology varied the most, the first topology was the best. So I wondered what the benefit of the second topology is? It was used fairly often in other designs. Second question: I noticed that sometimes high Vth devices are used for cascode. Is this due to there low Ioff current (reducing the overall leakage current of the mirror)? If so, then why not use high Vth for the mirror transistors as well?

Thnx in advance!

the 2nd one is better for low -voltage biasing than the first...

When you have two transistors in series with gates shorted like in the 2nd topology it is like one transistor with L=L1+L2. In this respect the 2nd topology is equivalent to a very basic mirror build with long transistors - usually the max L in advanced technologies is limited and to go beyond that limit one stacks transistors like that. This way you get relatively high output impedance without the trouble of designing a cascode. But since it is a simple mirror, its current variation is the worst.
Having a thick oxide cascode device is of course good for leakage. Another reason could be to protect the thin oxide device from over voltages.

Ok, thanks for the replies. Sutapanaki, I understand your explanation about increasing the maximum L by stacking. However I did noticed in other designs that the cascode transistors are indeed large L's, but the mirror transistors are 2 a 3 times minimum L (unfortunately the designer doesn't work here anymore, so I can't ask his motivations).

Hello sutapanaki,

is there any other motivation to stack transistors instead of using a single device with large L, apart from max L limitation.
Will there be a reduction in parasitics by stacking transistors of lower length as opposed to a single big L transistor?

Here is what I think. Suppose you have L=L1+L2 and L1=L2 for the sake of example. Let's have a transistor W/L. We have under consideration two choices.
1. Lay out a regular transistor W/L but split it, say, in two fingers of W/2/L and take the drain from the middle. If the active region between the two fingers' poly is wide X, then the junction cap (the bottom of the active, I'm not taking into account the sidewalls for simplicity) will depend on area X*W/2.
2.Split the transistor W/L into two series connected transistors each W/L1 as in the mirror we're talking about. Take the output of the mirror from the drain of the top transistor. Say the active region of that top transistor is again wide X. Then the junction cap of that drain (again bottom part only) will have area X*W.

Looks like the second option has higher parasitic capacitance. I also think the side wall capacitance for the 1st option will be smaller since it terminates (at least partially) into the channel on both sides of the drain area, while in the 2nd option only one sidewall will terminate in the channel but the other one is completely terminated in the bulk.
Maybe the fringe capacitance from the drain to the poly gate will be comparable in both cases.

so parasitic wise a single big L transistor may be better than stacked smaller L series transistors?
also, I read that longer length transistors have more threshold variation...which I do not
quite understand...

learning_curve said:

I read that longer length transistors have more threshold variation

Click to expand...

Due to the back-gate or body effect, which has a greater influence at long transistors.

I think the reason for using hvt devices in mirrors is used to reduce the the leakage ( gate leakage) .... correct me if am wrong

Hi,
Some of the technology only support high Vt transistor and want to operate from 1.5V to 5V.
We have such in our company, which also has nhvnative transistor with almost 0 Vt.
Then we can use the topology 2 with top transistors as nhvnative and bottom mirroring transistor as HV nmos.
By this we get the advantage of cascode transistor(for increasing gain) and also no additional leg reqd for Vb generation.

Hope this helped.

Supreet

Hello

the first topology has practically the highest output impedance that make the output current more stable, the third one is supposed to have the same output impedance but actually i simulated that and i found it has less than the cascode. but the advantages of the third one over the cascode is it has less minimum voltage so it extensively used , any way it consume more power and it need more transistor than the cascode.

the second mirror in your image I have no idea about it

maxporter said:

Hey all,

I'm currently looking at various current mirror topologies. Take a look at attached picture. The first ("normal" current mirror) and third (low voltage cascode mirror) are described in Razavi's book. The second I have stumbled upon looking at other designs. Curious about there performance, I simulated all three topologies: M1/M3 rather large W/L ratio and M2/M4 rather low W/L ratio. The output current of the second topology varied the most, the first topology was the best. So I wondered what the benefit of the second topology is? It was used fairly often in other designs. Second question: I noticed that sometimes high Vth devices are used for cascode. Is this due to there low Ioff current (reducing the overall leakage current of the mirror)? If so, then why not use high Vth for the mirror transistors as well?

Thnx in advance!
View attachment 80331

Click to expand...