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sigma delta fractional pll synthesizer

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franticEB

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Hi,
I have to realize in VHDL a frequency synthesizer in order to generate frequencies from 5Khz to 20Khz with 1Hz step or more if not possible so fine frequencies.
This is the scheme:


The N divider is made in VHDL(others are external components) but it permits only integer division.

With the help of internet i find fractional pll that has the drawback of spurios injection. The solution proposed is sigma delta fractional pll as in the image below.


I don't understand how it could be implemented in VHDL, and also what are inputs and output of sigma delta modulator.

the pld is Actel 42MX

Could you help me? Is there other solutions?
 

You could check out this guy's stuff: **broken link removed**

And yes, lots of own work required. :p But you can learn a lot just by going through his design iterations and lessons learned.
 
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