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Simple verilog question- divide real number by register value

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h@ro

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Hi all, I think this is a fairly trivial question for those experienced in verilog design, but I haven't been able to find any explicit answers

I'm writing a module where I am calculating frequency of an incoming signal, by first counting the number of clock cycles between change state of incoming signals. The number of clock cycles is stored in a 32 bit register "count [31:0]". To find find frequency, I use the function "frequency =6E-1/(20e-9 * count)" however when I try to compile this in quartus, I get "real numbers are not supported" and "real variable data types not supported". I can put 6E-1/20e-9 into a register, and divide a register by a register which can be compiled, but uses a huge amount of CPLD resources after quartus automatically infers a divider from the megafunction library.

So my question is how can I divide a real number by the number stored in the register using verilog?
 

I can put 6E-1/20e-9 into a register, and divide a register by a register which can be compiled, but uses a huge amount of CPLD resources after quartus automatically infers a divider from the megafunction library.
You mean you convert the real factor to an unsigned number and divide it by the measured number of clock cycles? That's basically the way to go. There are two ways to reduce the resource requirements:

- reduce the measurement resolution if applicable, e.g. 1 kHz or 100 Hz instead of 1 Hz.

- use a slow bitserial instead of a fast parallel divider. Period measurement is slow by nature, frequency calculation doesn't need to be faster
 

Although when using the divider megafunction I am not able to get the division to work when I simulate the design- I think the problem is I'm trying to use non integer numbers such as 20e-9? If that's the case then how would I divide, or even multiply by a non integer number - e.g. 2.65?
 

I don't understand the problem, 0.6/20e-9 = 30000000, so you can easily rewrite the calculation as integer division.
 

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