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I wanna know more deeply about synthesis

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tseelee

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My implemetation has 1.2million gates so i wanna optimize it. How?


First you should know more abot the rules of this forum. Read and follow them. Post in the appropriate forums, or you'll be warned. Topic moved.
/pisoiu
 

wrong place to ask question. You should ask at this forum
 

Preassuming that the complexity of your design is fairly average, optimization won't be an easy task. If you are using Synopsis Tools for sythesis and optimization, the book "Advanced Asic Chip Synthesis" Himanshu Bhatnagar Can be helpfull. You can download the e-book in this forum, you need to search.
Optimization of a design is veri skillfull job. Since you haven't mentioned many of the parameters, like complexity, targeting parameters like requency/area and time you have for this activity, it's difficult to comment.
 

Some ideas:
- Partitioning (Partition the design into smaller blocks & do bottom up synthesis)
- Over constraint your design, ie timing or area
 

ken_ooi said:
Some ideas:
- Partitioning (Partition the design into smaller blocks & do bottom up synthesis)
- Over constraint your design, ie timing or area
Click to expand...

The problem of tseelee is too many gate counters, so do not over constraint the

timing, this will increment the area.

The best way reduce area is modify your RTL code if the code not freeze yet.
 

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