Btrend
Advanced Member level 1
sigma delta adc 14 bit architecture
There is always difference between theoretical & pratical limit in analog IC design.
Could someone give me some figure or estimation about the degradation of sigma delta ADC/DAC from the ideal (theoretical) SNR calculation using different architecture as shown below?
I found the SNR estimation in text book as:
[Modulator (MOD) , Oversampling Ratio (OSR)]
In theorey:
MOD order =2, OSR=128 ==> SNR ~ 95db ==> 15 bit
MOD order =3 , OSR=128 ==> SNR ~ 120dB ==> 19 bit
Real IC implementation :
MOD order =2, OSR=128 ==> SNR ~ ---- db ==> -- bit
MOD order =3 , OSR=128 ==> SNR ~ ---- dB ==> -- bit
There is always difference between theoretical & pratical limit in analog IC design.
Could someone give me some figure or estimation about the degradation of sigma delta ADC/DAC from the ideal (theoretical) SNR calculation using different architecture as shown below?
I found the SNR estimation in text book as:
[Modulator (MOD) , Oversampling Ratio (OSR)]
In theorey:
MOD order =2, OSR=128 ==> SNR ~ 95db ==> 15 bit
MOD order =3 , OSR=128 ==> SNR ~ 120dB ==> 19 bit
Real IC implementation :
MOD order =2, OSR=128 ==> SNR ~ ---- db ==> -- bit
MOD order =3 , OSR=128 ==> SNR ~ ---- dB ==> -- bit