sonofflynn
Junior Member level 2
I am getting hold time violations when simulating a design in NC-Verilog. The error message looks like this:
Warning! Timing violation
$setuphold<hold>( posedge CK &&& (flag == 1):120 NS, negedge D:120 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: ../synth/ibm18.v, line = 6410
Scope: testHarness.mcounter.\rstPipe_reg[0]
Time: 120 NS
The design was synthesized using Design Compiler and the 'report_qor' command said that there were no timing violations. Does anyone know what I should do to fix this?
Warning! Timing violation
$setuphold<hold>( posedge CK &&& (flag == 1):120 NS, negedge D:120 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: ../synth/ibm18.v, line = 6410
Scope: testHarness.mcounter.\rstPipe_reg[0]
Time: 120 NS
The design was synthesized using Design Compiler and the 'report_qor' command said that there were no timing violations. Does anyone know what I should do to fix this?
