Looking for materials on designing 24 second counter VHDL

XWaterpolo · Aug 30, 2012

I'm beginner in VHDL and was asked to construct a 24 second counter with 50 Hz input. I designed it on paper with two counters, one modulo-24 counter using modulo-32 and the other is modulo-50 using modulo-64.

I started writing the codes for both separately. The first counts to 50 aka 1 second and initializes the second one to start.
But I do not know how to combine them both since I will need the CLK_1 to be "1" when the second counter reaches "110010".

Maybe you can forward me some material where combining counters is easy to understand

barry · Aug 30, 2012

It's not really clear what your desired output is. Do you want a pulse every 24 seconds? Do you want a pulse every second? From your description, I'm not sure why you need 2 counters. If you have an 11-bit counter, you can count 1200 pulses (50Hz x 24) and decode the output.

XWaterpolo · Aug 31, 2012

barry said:
It's not really clear what your desired output is. Do you want a pulse every 24 seconds? Do you want a pulse every second? From your description, I'm not sure why you need 2 counters. If you have an 11-bit counter, you can count 1200 pulses (50Hz x 24) and decode the output.

I need to count to 24 with a given 50 Hz clock signal (0.02 seconds). That is why I am using a 5-bit and 6-bit counter. And yes, I need to generate a pulse every second.

Nice idea with the 11-bit counter :grin: (5+6 haha).

So if I generate 1200 pulses on 50 Hz, I will theoretically get 24 seconds. It is the same as having a 6-bit counter count to 50 to convert 50 Hz to 1 Hz in order for the 5-bit counter to count to 24, right?

sakthikumaran87 · Aug 31, 2012

See from your spec, you have a 5oHz clk -> 0.02s period => 1200 clk cycles will account for your 24s need. Now converting 1200 into binary format provides 10010110000 which is a 11-bit no. Hence the 11 bit counter comes into picture. Now you can input your clk and make the counter count till 10010110000 which will be equal to 24s.

barry · Aug 31, 2012

sakthikumaran87 said:
See from your spec, you have a 5oHz clk -> 0.02s period => 1200 clk cycles will account for your 24s need. Now converting 1200 into binary format provides 10010110000 which is a 11-bit no. Hence the 11 bit counter comes into picture. Now you can input your clk and make the counter count till 10010110000 which will be equal to 24s.

Or, you can load your counter with 1001010111(1199 decimal) and count DOWN to zero. When all 11 outputs are zero, you set a flag, and then reload the counter on the next clock. This way, the 24 second flag and counter load signal are the same. (Remember, you have to load your counter with 1 less than your number of counts because zero is a number-e.g., if you count from 2, you are actually dividing by 3).

XWaterpolo · Aug 31, 2012

Yeah I know what to do now. I was actually writing the code for 2 counters separately but now I see that only one is needed.
It can count both ways (up to down or vice versa) and then it resets/loads.

Thanks again you guys, I will post the code once I am finished (could take a while with all obligations)

XWaterpolo · Aug 31, 2012

Just one more thing I want to ask

Since I will need to display the passing seconds (1,2,3 ...) on a LED display, will they show between 1 Hertz apart or will the number be something like 50 after 1 second (since the counter is loaded with the value of 50 after 1 sec)?
If it is not, then I will have to go back to my 2 counters design in order for the second to display the passing seconds properly

barry · Aug 31, 2012

That's COMPLETELY DIFFERENT than your original 'I need a 24 second counter' post!!! You are wasting our time when you don't ask the right question. It's not just "one more thing" it's a whole different thing.

XWaterpolo · Sep 1, 2012

barry said:
That's COMPLETELY DIFFERENT than your original 'I need a 24 second counter' post!!! You are wasting our time when you don't ask the right question. It's not just "one more thing" it's a whole different thing.

Yes I know. That is why I was talking about 2 counters at the beginning. Still tricky idea with the 11 bit counter.

I wrote the code for the 2 counters separately but I still do not know how to combine them so that the Clock Enable signal of the second one (modulo 24) will be dependent on the Reset value (modulo 50) of the first one.

mrflibble · Sep 1, 2012

So make a 6-bit counter that does 50 counts at a 50 Hz rate for your seconds. And everytime this counter wraps you count down your completely different and also separate 5-bit counter for the 24 seconds. Send the content of this 24 second counter to your display and you're done.

XWaterpolo · Sep 1, 2012

mrflibble said:
So make a 6-bit counter that does 50 counts at a 50 Hz rate for your seconds. And everytime this counter wraps you count down your completely different and also separate 5-bit counter for the 24 seconds. Send the content of this 24 second counter to your display and you're done.

On paper, I did that.
I have written both the codes separately and they work independently. But I am kind a newbie in VHDL and do not know how to "inform" (Clock signal = Enable) the second counter that the first one completed his count to 50

mrflibble · Sep 1, 2012

Time to un-newbie yourself by some reading then.

When the 50 Hz counter counts down you generate a pulse that is high for 1 clock. Use that as the clock enable for your 2nd counter.

XWaterpolo · Sep 3, 2012

So I wrote the code for both and they work perfectly separated.

Here it is for the Clock Generator counter that counts to 50 with a wait for 10000 us at the TestBench

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity count64 is
    Port ( clk : in  STD_LOGIC;
           enable : out  STD_LOGIC;
           reset : in  STD_LOGIC;
           q64 : out  STD_LOGIC_VECTOR (5 downto 0):="000000");
end count64;

architecture Count_50 of count64 is
signal sostojba : std_logic_vector(5 downto 0):="000000";
begin

countingTo50: process(clk,reset)
begin
if reset='1' then
sostojba <= "000000";
elsif(clk'event and clk='1') then
		   sostojba <= sostojba+1;
end if;
if sostojba="110010" then
 sostojba <= "000000";
 enable:='1';
else enable:='0';
end if;
end process;
q64 <= sostojba;
end Count_50;

I need somehow to pass the argument "enable" to the second counter.
Should I put this module and its component in a package and then use it in the Architecture of the second counter?
Or is there a simpler way?
I want to find out the tricks for passing arguments between modules but I could not find anything so far to resemble a code of that functionality

D.A.(Tony)Stewart · Sep 3, 2012

A better description of problem may be... I need a 24 second timer, my input is 50Hz and my outputs are 1 PPS with LED "seconds" counter display. The counter should stop after 24 seconds. and requires a reset input to repeat. I am asked to implement this in VHDL.
My question is ....

FYI if you need specific pulse width on any counter outputs , this is usually determine by input clock rate or gating output with latch and reset when needed.

There are up or down counter & synchronous or asynchronous (ripple) counters, each with pro's and con's for simplicity vs speed.
Cyclic mode of counter may determined by BCD or binary preset for down counters or reset and count UP to match desired output to reset on next clock pulse.

these are just general modes of counters for hardware or software.

XWaterpolo · Sep 3, 2012

SunnySkyguy said:
A better description of problem may be... I need a 24 second timer, my input is 50Hz and my outputs are 1 PPS with LED "seconds" counter display. The counter should stop after 24 seconds. and requires a reset input to repeat. I am asked to implement this in VHDL.
My question is ....

FYI if you need specific pulse width on any counter outputs , this is usually determine by input clock rate or gating output with latch and reset when needed.

There are up or down counter & synchronous or asynchronous (ripple) counters, each with pro's and con's for simplicity vs speed.
Cyclic mode of counter may determined by BCD or binary preset for down counters or reset and count UP to match desired output to reset on next clock pulse.

these are just general modes of counters for hardware or software.

The counter resets after 24 seconds. It does not require to be so specific for outside reset/enable. I need something that works like a modulo-24 with 50 Hz input.

Can you assist me with how to "inform" the second counter?
Since I tried implementing the counter which goes to 50 as a COMPONENT in the architecture of the second one (and mapping it) but it did not work

XWaterpolo · Sep 7, 2012

Thanks @mrflibble for your help
I just needed the simulation to go right

Modulo 50 Counter

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
   entity count64 is
      Port ( clk : in  STD_LOGIC;
           enable : inout  STD_LOGIC;
           reset : in  STD_LOGIC;
           q64 : out  STD_LOGIC_VECTOR (5 downto 0):="000000");
   end count64;


	architecture Count_50 of count64 is
		signal sostojba64 : std_logic_vector(5 downto 0):="000000";
	begin
		countingTo50: process(clk,reset)
			begin
				if reset='1' then
					sostojba64 <= "000000";
				end if;
				
				if(clk'event and clk='1') then
					sostojba64 <= sostojba64+1;
				end if;
				
				if sostojba64="110010" then
					sostojba64 <= "000000";
					enable<='1';
				else enable<='0';
				
				end if;
			end process;
		q64 <= sostojba64;
	end Count_50;

Modulo 24 Counter

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;


entity count24 is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           q32 : out  STD_LOGIC_VECTOR (4 downto 0):="00000");
end count24;

architecture Count24 of count24 is
	signal sostojba32: std_logic_vector(4 downto 0):="00000";
begin
		  process(clk,reset)
		  begin
			if reset='1' then
			  sostojba32 <= "00000";
			elsif (clk='1' and clk'event) then
				  sostojba32 <= sostojba32 + 1;
			end if;
			
			if sostojba32 = "11000" then
			  sostojba32 <= "00000";
			end if;
		  end process;
   q32 <= sostojba32;

end Count24;

And the TestBench

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY count50_test IS
END count50_test;
 
ARCHITECTURE behavior OF count50_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT count64
    PORT(
         clk : IN  std_logic;
         enable : INOUT  std_logic;
         reset : IN  std_logic;
         q64 : OUT  std_logic_vector(5 downto 0)
        );
    END COMPONENT;
	 
	 COMPONENT count24
	 PORT(
			clk: in std_logic;
			reset: in std_logic;
			q32: OUT std_logic_vector(4 downto 0)
			);
	 END COMPONENT;
    

   --Inputs
   signal clk1 : std_logic := '0';
   signal reset : std_logic := '0';

	--BiDirs
   signal enable : std_logic;

 	--Outputs
   signal q64 : std_logic_vector(5 downto 0);
	signal q32: std_logic_vector(4 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ms;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: count64 PORT MAP (
          clk => clk1,
          enable => enable,
          reset => reset,
          q64 => q64
        );
		  
	uut1: count24 PORT MAP(
	       clk=> enable,
			 reset => reset,
			 q32 => q32
			 );

   -- Clock process definitions
   clk_process :process
   begin
		wait for clk_period;
		clk1 <= not clk1;
   end process;
END;

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