dksagra
Junior Member level 1
I need one help. Please if you able to help me i will be very grateful for your kind help.
There is one tool in Xilinx, System Generator.
I have prepare one architecture using blocks from Simulink in it. i am getting good results
then i have generate the VHDL code through HDL CODE GENERATION.
now i have a VHDL code of the same architecture.
my question is: Now i have to apply Partial Reconfiguration on this VHDL code. So Can we apply?
if yes then how can be?
I am looking forward to your reply.
There is one tool in Xilinx, System Generator.
I have prepare one architecture using blocks from Simulink in it. i am getting good results
then i have generate the VHDL code through HDL CODE GENERATION.
now i have a VHDL code of the same architecture.
my question is: Now i have to apply Partial Reconfiguration on this VHDL code. So Can we apply?
if yes then how can be?
I am looking forward to your reply.
