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Signal distortion on Altera Apex output

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giggs11

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hi all,

I'm trying to output data from a design I implemented on the Altera APEX FPGA. When I analyze the data that is outputted from the pin, there seems to be distortion and the data that is outputted is wrong. The data connected to the output pads of the pins are directly from a register. So it can be assumed stable between clock edges.

My question is: could the noise be due to the IO standard I'm using, which is LVTTL. Could it be improved if i'm using LVCMOS or some other standard. Is there anyway due to reduce the risk of data being distorted when being outputted from the FPGA chip.

Thanks in advance.
 

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