BartlebyScrivener
Member level 5
I am working through some tutorials on the National Instruments website for the NI Digital Electronics FPGA board.
**broken link removed**
I understand the verilog apart from one little bit in all of the modules where a delay has been put in of #2 in various places, however when I synthesise I get the following error
So what is the point of putting delay in? What does it actually mean?
Thanks.
**broken link removed**
I understand the verilog apart from one little bit in all of the modules where a delay has been put in of #2 in various places, however when I synthesise I get the following error
Code:
WARNING:Xst:916 - "seven_segment.v" line 36: Delay is ignored for synthesis.So what is the point of putting delay in? What does it actually mean?
Thanks.
