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How to use CADENCE IC to measure PLL lock time

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esibobo

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I'm using Virtuoso 6.1.4. I have a working PLL, and i would like to determine how long it takes the PLL to acquire lock after the reference frequency is altered from the minimum to maximum (or from any reference frequency to another for that matter). I'm not too conversant with cadence and would like some help on how to go about simulating this scenario.
Thanks.
 

Set the VCO control voltage to zero and measure the locking time with a transient simulation.
 

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