Accessing DDR2 RAM on Digilent Atlys board

Hello,
I'm working on a video-processing project. I've been able to program the FPGA and write to the SPI Flash for automatic booting.
Now, I'm trying to exercise myself on accessing the DDR2 128 Mbit RAM on Atlys board (Spartan6-based); which is one of the key-component for the final application (I want to use it as a framebuffer for retrieving the HDMI source).
But, to begin with... my idea is to create a simple example that works like this:
-every time user changes a switch, buttons status are written at a certain address in the RAM; The same values, then, are just read from the RAM and sent to the LEDs...

What I miss is the "know-how" to operate the RAM...
Can you guys suggest me some tutorial/guides/hints?
Thank you

This is a nice starting point: https://tristesse.org/FPGA/XilinxMIGTutorial

Thank you.
I understood that I need to use the integrated Memory Controller Block to access the external RAM; now I will try to run the example
BTW I found some weirdness:
Xilinx advertises Spartan 6 as having 2 MCBs:
http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
[pag 2, see row XC6SLX45 which is that of Atlys board...]

but on Atlys schematics:
http://www.digilentinc.com/data/products/atlys/atlys_c2_sch.pdf
[pag 9] I see there is only one (on Bank 3) which is directly connected to the external DDR RAM...
I mean.. wasn't the XC6SLX45 supposed to have two Memory Controller Blocks? I see only one.. so where is the second?

-Second thing:
is this FPGA a -3 speed grade or -2 speed grade?
In the example I downloaded from the provided link, the project was configured as -3 grade (xc6slx45-3csg324), but
on the schematics ( http://www.digilentinc.com/data/products/atlys/atlys_c2_sch.pdf at pag 9), the FPGA chip is indicated as
"xc6slx45-2csg324c", so I would assume is -2 speed grade

Elektronman said:

Thank you.
I understood that I need to use the integrated Memory Controller Block to access the external RAM; now I will try to run the example
BTW I found some weirdness:
Xilinx advertises Spartan 6 as having 2 MCBs:
http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
[pag 2, see row XC6SLX45 which is that of Atlys board...]

but on Atlys schematics:
http://www.digilentinc.com/data/products/atlys/atlys_c2_sch.pdf
[pag 9] I see there is only one (on Bank 3) which is directly connected to the external DDR RAM...
I mean.. wasn't the XC6SLX45 supposed to have two Memory Controller Blocks? I see only one.. so where is the second?

Click to expand...

The second is in the category of "present in the fpga, but unused on this particular board because we only needed 1 controller".

-Second thing:
is this FPGA a -3 speed grade or -2 speed grade?
In the example I downloaded from the provided link, the project was configured as -3 grade (xc6slx45-3csg324), but
on the schematics ( http://www.digilentinc.com/data/products/atlys/atlys_c2_sch.pdf at pag 9), the FPGA chip is indicated as
"xc6slx45-2csg324c", so I would assume is -2 speed grade

Click to expand...

I've e-mailed Digilent some time ago to ask precisely that. The reply was that it's a speed grade 2. However in the BSB files from Digilent it says speed grade 3. So that's a bit confusing. I am working under the assumption that it's a speed grade 2 as per the e-mail response.

I wouldn't trust the schematics too much - there are a few things that are COMPLETELY different to what you get on the board

Unless you are developing a very high performance application, it's probably good to be conservative and specify the slower part. If you need maximum performance, all you can do is try and see what happens. If the design fails to work reliably, especially when the FPGA gets warm, you might be having timing problems related to a slow part.