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Why PLL input and output clocks are treated asynch in STA ?

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mr_vasanth

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Can someone please help me understand why PLL input clocks and output clocks are treated as asynchronous to each other in static timing analysis ? Should not we say that they are synchronous since the output clock phase of a PLL is always locked with the input clock ?
 

I do not think there is any path interaction between in input clock and output clock.
 

Some simple PLL will not grant the phase match between the PLL input_clk and the PLL output_clk (just the two will phase match at the phase detector within the PLL itself).
While some special designed PLL with phase shift and delay line in it will implement phse management function, then the output clock and the input clock will have some phase relation.
So, you have to refer to the PLL doc or the designer for more info.
 
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