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[SDC] What type of timing constrains stored @SDC?

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ivlsi

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[SDC] Input/Output delays + PVT corners @SDC

Hi All,

What type of timing (or other) constrains will be stored in the SDC file after the synthesis?

Will the input/output constraints be stored in the SDC file? If I read Netlist of sub-modules to the Top hierarchy, how should I constraint interfaces between the sub-modules? Will synthesizer continue to optimize the sub-module netlists if they already meet timing and other constraints?

Should separate SDC files be created for different PVT/OCV corners?

Thank you!
 
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whatevever tyou loaded during synthesis or for synthesis should be exported back in the SDC file post synthesis.
Yes, IO delays will be stored as well.

Once you integrate thesubmodules to top herachy you need to have constraints for the top module and then perform optimization. Depending on that the interfaces will be optimized. If no constraints are applied it is as good as unconstrained

Yes - usually there are different files created for different modes and corners.
 

1. SDC : The tool will store below information in SDC .
1. Clocks and generated clocks.
2. Load and max slew values
3. Driving cell
4. IO delays.
5. Timing exceptions ( Max/Min delays, False paths and Multi cycle paths).

2. The reason for bottom up synthesis , not to synthesize the hierarchical modules when you integrate the top level design.
The glue logic between the sub modules only need to synthesize during the top level synthesis. The constraints need to apply for this. The sub modules need to put dont touch attribute to it.

If you synthesize the sub modules in the top level synthesis, there is no value addition for bottomup synthesis.

3. PVT/OCV corners :
- SDC should be different for modes(func ,Scan or TFT etc), not for corners.
- Corner mode SDC is required when extreme temparatures are used to find the sustainability. Its very rare.

Usually, we avoid differnt SDC for differnt corners. FYI, Do we need separate SDC for temaparature ranges for 125c and -40C ?. Definitily No.

OCV corners SDC : No. We dont need differen SDC for different OCV derates.
 

sam536

I agree with 1 and 2 but have a different view on (2) - not that your wrong but that is not the only reason.
Bottom-up is also done to parallelize effort towards the top module and also help close reg2reg paths faster with a more focussed approach. As of today I see bottom-up only for more chanllenging designs in terms of TAT or huge instance / gate count

Also the value addition that top level will still provide when you do link it up again is constant propagation across hierarchies or from Top level.
 

SDC file contains clock definition,generated clock,clock latency(Source+Network)latency,Clock uncertainity(Skew+Jitter,Margin),False path,Multi cycle path,Multi frequancy path,crtical path,half cycle path,input delay,output delay,min,max delay
 

top level will still provide when you do link it up again is constant propagation across hierarchies or from Top level.

Is there a special command, which make the constraints be propagated through the hierarchies? What's the command? What cases should be used?

BTW, I recently was attended an interview in one of the big semiconductors company and was told by a CAD manager that they don't use 'dont_touch' attributes in their synthesis flow. He even told me they don't use bottom up flow at all - and they do chips of millions gates each one! Very strange... What do you think? It was Intel :)
 
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PVT/OCV corners :
- SDC should be different for modes(func ,Scan or TFT etc)

Is this for STA or Synthesis? How do different Input/Output delays (for example) might be applied on the same I/O pins? I understand it might be done for STA purposes... But what's about the synthesis? How should the Input/Output constraints be evaluated for different modes?

Thank you
 

@dmitryl

There are no specific commands to propagate constants - its just that your boundary optimization, constant propagation should be enabled during synthesis.
On dont_touch i agree partly - cuase the main aim of synthesis is to optimize which dont_touch prevents - but it is required at times to preserve some secure logic or some test logic even though it is redundant and may be connected later in the flow.

Well depends on the design cycle time if they can have the schedule enough to go for a top down with millions of gates - i would say it is good.

In synthesis as well you can have two SDC's func and test and optimize the design for both the modes

Hope this helps...
 

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