ivlsi
Advanced Member level 3
[SDC] Input/Output delays + PVT corners @SDC
Hi All,
What type of timing (or other) constrains will be stored in the SDC file after the synthesis?
Will the input/output constraints be stored in the SDC file? If I read Netlist of sub-modules to the Top hierarchy, how should I constraint interfaces between the sub-modules? Will synthesizer continue to optimize the sub-module netlists if they already meet timing and other constraints?
Should separate SDC files be created for different PVT/OCV corners?
Thank you!
Hi All,
What type of timing (or other) constrains will be stored in the SDC file after the synthesis?
Will the input/output constraints be stored in the SDC file? If I read Netlist of sub-modules to the Top hierarchy, how should I constraint interfaces between the sub-modules? Will synthesizer continue to optimize the sub-module netlists if they already meet timing and other constraints?
Should separate SDC files be created for different PVT/OCV corners?
Thank you!
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