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Gate Level Simulation issues.

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Nisha1990

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hi all..i am running GLS and getting error due to "X" in control signal...when i trace it back, i reach flop having a corrupted clock and enable and input is initially "x" then settles to a value and again goes "x". When i trace back these signal i end up in a loop...can somebody guess what might be the issue ??
 

Are you having icg in path ? If yes intialize icg randomly and it should be fine.
 

And for DFF with both Q and QN output, you have to random initial Q/QN with opposite value. For example: (Q = 0 and QN =1) or (Q = 1 and QN = 0)
Thanks.
 

Is this clock generated out from the CLKGEN ckt?. From your description, there is control logic to generate the clock to your ckt.
Follow these steps to find the root cause ?.
I assume tool used for signoff is synopsys.
Ask your timing engineer to trace the fanin of the clock. (report_transisitve_fanin -to <your clock pin).
Trace the signal back and make sure there are no Setup/hold violations to fanin of the clock signal.
If you dont have STA violations, To find the setup issue, Run GLS for 1Mhz clock and check the timing.


Do these checks and still problem exists, please let us know.

Regards, Sam
 

Which tool you are using ?
 
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