ishailesh
Junior Member level 3
- Joined
- Apr 4, 2012
- Messages
- 31
- Helped
- 6
- Reputation
- 12
- Reaction score
- 6
- Trophy points
- 1,288
- Location
- New Delhi, India
- Activity points
- 1,652
Hey all
Mine board is Virtex2Pro. I want to drive a stepper motor from FPGA.
I am using L293D as the driver circuit.
So for that i designed a state machine which changes its output on each rising edge of the clock.
The Clock Speed is 100MHz (Internal Clock). But somehow i am not getting the desired pulses at the output.
Here is my code.
I was successfully able to program the fpga. But it didn't produce the desired result.
So please help.
Thanks and Regards
Mine board is Virtex2Pro. I want to drive a stepper motor from FPGA.
I am using L293D as the driver circuit.
So for that i designed a state machine which changes its output on each rising edge of the clock.
The Clock Speed is 100MHz (Internal Clock). But somehow i am not getting the desired pulses at the output.
Here is my code.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 library ieee; use ieee.std_logic_1164.all; entity motor_state is port( en : in std_logic; clk : in std_logic; dir : in std_logic; reset : in std_logic; data_out : out std_logic_vector(3 downto 0) ); end entity; architecture motor_state_sequential of motor_state is -- Build an enumerated type for the state machine type state_type is (s0, s1, s2, s3); -- Register to hold the current state signal state : state_type; begin -- Logic to advance to the next state process (clk, reset) begin if (en = '1')then if reset = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0=> if dir = '1' then state <= s1; else state <= s3; end if; when s1=> if dir = '1' then state <= s2; else state <= s0; end if; when s2=> if dir = '1' then state <= s3; else state <= s1; end if; when s3 => if dir = '1' then state <= s0; else state <= s2; end if; end case; end if; end if; end process; -- Output depends on the current state process (state) begin if (en = '1')then case state is when s0 => data_out <= "0001"; when s1 => data_out <= "0100"; when s2 => data_out <= "0010"; when s3 => data_out <= "1000"; end case; end if; end process; end motor_state_sequential;
I was successfully able to program the fpga. But it didn't produce the desired result.
So please help.
Thanks and Regards
Last edited by a moderator: