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VHDL to Schematic caaaadence flow

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darockdr

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Hello

I have a vhdl file (behavioral .. if then ...) that i would like to synthesize with specific logic gate from my cadence Design Kit library.

I am not sure where to start, it would be great if someone can direct me or show me the flow to do that .

my vhdl is only combin logic but i don't know how to link it to my Cadence DK library ?

Please, help.

Best,

David
 

Dear darockdr,

logic synthesis with Cadence tools is performed using Encounter RTL Compiler. To perform synthesis you need to provide the tool with the following information: list of HDL files composing your design, top-level entity (while launching the synthesis script), absolute path to the technology library of interest and, in case you have sequential circuits, timing constraints. This is done in a TCL/TK script. What I suggest you is to take a look at the Encounter RTL Compiler documentation that provides a lot (really a lot) of information on this topic.

Cheers
 

Thanks kingslayer, I am having a license issue with encounter, but thank you for the steps to follow ! that was exactly what i needed.

I ll get back to you as soon as i can start playing with encounter !

Best,

David
 

Your company (or university) must have Cadence license. Assuming that you have access to a license, you should check with the Cadence License Manager to get the idea on how to setup your environment. Generally, if your university has a license file on a network, it is enough to setup license variable.

Cheers
 

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