shaiko
Advanced Member level 5
My FPGA is a "pass through hub" for 3 pairs of Tx and Rx signals between 2 devices called: HOST and UUT.
Each Rx/Tx pair has it's own control signal.
When the control signal is '1' the corresponding Tx is connected to Rx and allows data to flow.
When it's '0' the FPGA drives logic '1' to the Tx.
Will the following loop do the job ?
Each Rx/Tx pair has it's own control signal.
When the control signal is '1' the corresponding Tx is connected to Rx and allows data to flow.
When it's '0' the FPGA drives logic '1' to the Tx.
Will the following loop do the job ?
Code:
mux : process
(
CONNECT_I ,
HOST_TO_FPGA_RX_I ,
UUT_TO_FPGA_RX_I ,
FPGA_TO_HOST_TX_O ,
FPGA_TO_UUT_TX_O
) is
begin
for index in 0 to 4
loop
if CONNECT_I ( index ) = '1' then
FPGA_TO_HOST_TX_O ( index ) <= UUT_TO_FPGA_RX_I ( index ) ;
FPGA_TO_UUT_TX_O ( index ) <= HOST_TO_FPGA_RX_I ( index ) ;
else
FPGA_TO_HOST_TX_O ( index ) <= '1' ;
FPGA_TO_UUT_TX_O ( index ) <= '1' ;
end if ;
end loop ;
end process mux ;
