[SOLVED] DRC error message: NW tiedown

I am using IBM .18u technology and keep getting this DRC error related to my nwells and have no clue how to fix it.

DRC error message:

(((NW not cover by GRLOGIC) or (NW touching BB)) touching ((PC over RX)) not over DN
must be tied down by the time M1 is complete.
valid tie down 1 : pdiff in NW is connected to ndiff in substrate by m1
valid tie down 2: ndiff in NW (ntap) is connected to ndiff in substrate by m1( or straddle NW edge)
valid tie down 3 : ndiff/pdiff in NW is connected to ptap in substrate by m1( or pdiff straddles NW edge)

Here is a screenshot. If I remove the RX rectangle connecting the two nwConts together, I get the error. If i leave it there, the error goes away. I'm not sure why this is happening..Both m2 rectangles are labeled vdd.

Re: DRC Error: NW tiedown

a simple way to fix this (antenna) error is to place a rectangle of RX straddling the NW (a portion will be inside NW, the rest will be in the pwell covering the substrate), this will create an n+ diode in the p-substrate and connect it to the NW potential. Get rid of everything else...

Re: DRC Error: NW tiedown

Dgnani,

Thanks for the help. One more question though. When I place an RX rectangle that is partially inside NW and partially not, I get this DRC error.

RX Nwell contact within NW (Where the RX Nwell contact straddling NW is prohibited) >= 0.0um.

I'm not quite sure what this means. Thanks.

Re: DRC Error: NW tiedown

Hi

the error is puzzling since this is one of the suggestions provided (valid tied down 2) to fix the original violation and also because it work in the very similar ibm 130nm process. In any case simply split the rectangle in two parts one all inside NW one in the external PW and connect them by M1, that should fix it

Re: DRC Error: NW tiedown

This worked. Thanks dgnani!

Hi, I'm using the same technology as u did. I got the DRC error: (GR131_ana violation)
((Gates not over TG) NOT covered by GRLOGIC) OR ((Gates not over TG) under QT MIM capacitor) must have a RX tiedown by M1 metal.

I tried to tiedown for PMOS in nwell by placing a cell(ptiedown) from the 7rf library and putting nwCont adjacent to PMOS. But it still doesn't work. I did the same thing for NMOS by placing a cell(ntiedown) and putting pwCont adjacent to NMOS. Here is my layout:
could u help me? Thanks so much