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[SOLVED] design a delay line for thesis

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paramis

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Hi,all
I am M.S. student of electrical engineering.I want to choise this subject for my thesis:
'' design a delay line with delay=2nsec on the chip"
Do you have any information about that?
 

lots of controlled impedance strip lines. Prop delay must be a controlled impedance for analog broadband, otherwise, most people try to get the delay out of the chip ;) Normally snake shaped tracks are used to offer proper delay for matching bus signals.
 
What is your idea about "Analog DLL"?
 

I can use 0.35u(3.3v) or 0.18u(1.8v) process.I don't have any information about load.
 

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