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why set the loop bandwidth 0.1~0.2 of the switch frequency in DCDC ?

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zhangyunwu5555

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Hi:
why set the loop bandwidth 0.1~0.2 of the switch frequency in DCDC ?
and i got two reasons: one is based on the sampling theorem, that bandwidth must smaller than half of the switch frequency ; and the other is the noise consideration.

Best wishes!
 

It's related to the switching frequency. You don't want the regulator loop feedback to respond to the switching frequency ripple voltage, but only to the low frequency average output voltage (which is what you are trying to regulate). Thus you want the loop gain to be very low at the switching frequency.
 
Hi crutschow:

Thanks a lot for your kindly help!

You don't want the regulator loop feedback to respond to the switching frequency ripple voltage
It is easy to understand from the bode of LOOP gain that the higher frequency the lower gain which is able to reject the amplify of the ripple voltage with the switching frequency.However, from the expression of ripple voltage,the higher the switching frequency the small the ripple voltage (IL/8*fs*C), which is independent of the loop gain!

And, there are some DC-DC chips which adopts the way of "ripple voltage regulate" , then what about their requirement of loop bandwidth?
 

It is easy to understand from the bode of LOOP gain that the higher frequency the lower gain which is able to reject the amplify of the ripple voltage with the switching frequency.However, from the expression of ripple voltage,the higher the switching frequency the small the ripple voltage (IL/8*fs*C), which is independent of the loop gain!

And, there are some DC-DC chips which adopts the way of "ripple voltage regulate" , then what about their requirement of loop bandwidth?
Naturally, the higher the switching frequency for a given output LC filter, the lower the ripple.

"Hysteretic" DC-DC converters do indeed use the ripple voltage to determine the duty-cycle of the switch for control of the loop. They do not need frequency compensation of the loop for stability, as standard control loops do, and thus do not have a "loop bandwidth" as such.
 
Hi cruschow:
great thanks for your immediate response!
Best wishes


Hi ZekeR:


you may be interested in reading this article describing ripple regulator loop gain.
the paper is discussed about the ripple regulators which use the hysteric comparators, and it is quite exist some ripple regulators that does not use a hysteric comparator, such as MC34063, and what do you think about these chips, and what factors did the designers think when they designed the 34063?

And ,would you mind to tell me why the ripple regulators have a improved transient response compared with the current mode or voltage mode controlled PWM chips?

Best wishes!
 
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As a rule of thumb a switching regulator introduces an average loop dead time of 0.5/fs. Thus the loop bandwidth limit is simply commanded by stability requirements.
 

.................
the paper is discussed about the ripple regulators which use the hysteric comparators, and it is quite exist some ripple regulators that does not use a hysteric comparator, such as MC34063, and what do you think about these chips, and what factors did the designers think when they designed the 34063?

And ,would you mind to tell me why the ripple regulators have a improved transient response compared with the current mode or voltage mode controlled PWM chips?
Hysteretic or ripple regulators have a relatively simple loop design but they require some ripple voltage on the output to operate. If you want minimum output ripple, then you want to go with a normal feedback voltage loop which doesn't depend upon ripple.

Ripple regulators have improved transient response because there is no frequency rolloff in the feedback loop to limit the response time to changes in the output voltage. The loop is designed to respond at the frequency of the switching frequency ripple.
 

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