Would it be possible to have DFT for FPGA based designs?

Hi,
Would it be possible to have DFT for FPGA based designs. I mean actually have scan chains??

fpga dft

DFT logic is used to test the chip for manfacturing/fabrication errors due to wafer contamination, variation in doping , shorts/open in silicon etc... since FPGA is already manfuactured and tested,,, DFT logic is not required in FPGA designs.

dft for fpga

I think you can insert DFT ciricuit into FPGA to test your designed circuits. JTAG circuit inherently in FPGA is used to test FPGA and for debug purposes.

Re: DFT for FPGA

videohu said:

I think you can insert DFT ciricuit into FPGA to test your designed circuits. JTAG circuit inherently in FPGA is used to test FPGA and for debug purposes.

Click to expand...

test for what?? well if u intend to check the circuit for functionality at different nodes in the circuit.. u can do that better by using software tools (like chipscope pro for xilinx). ok anyway suppose u insert the scan chain into FPGA logic how ill u test it...(ATEs which cost millions of dollars pump the ATPG patterns and analyze the results incase of ASIC testing) if u intend to do this process manually..... I guess it will be very very difficult

DFT for FPGA

If idea is to use backanotated netlist (after scan chain insertion) for FPGA prototyping, you could try to find famous Foster-Benning book, they cover this matter.
From my point of view, there are some advantages in this instead of using RTL for FPGA (like testing of design which really going into chip after all toll changes, ECOs, ...).
But dis-advanteges are that you need to develop scripts for backanotation, FPGA area utilization will be poorer due to replacement of ASIC library with FPGA target library instead of pure RTL, ...

Of course, FPGAs are pretested and you don't need any scanchain for functional purpose on it.
But, if you use aprouch with back-anotated netlist, you could run your ATPG tests on FPGA to post-verify all transformation in front- and back-end flow.