The setup violation for the inclkSrc2reg paths in the layout designed by encounter

Hi everyone,
I am a learner of encounter (cadence) and meet the setup violation on the inclkSrc2reg group, which is shown as follows:


Path 1: VIOLATED Setup Check with Pin \DFF_1048/Q_reg /CLK
Endpoint: \DFF_1048/Q_reg /D (^) checked with leading edge of 'CK'
Beginpoint: g35 (v) triggered by leading edge of 'CK'
Path Groups: {inclkSrc2reg}
Other End Arrival Time 0.582
- Setup 0.190
+ Phase Shift 5.000
- Uncertainty 0.100
= Required Time 5.292
- Arrival Time 13.369
= Slack Time -8.077
Clock Rise Edge 0.000
+ Input Delay 0.200
+ Drive Adjustment 0.717
= Beginpoint Arrival Time 0.917
Timing Path:
+------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required |
| | | | | | Time | Time |
|-----------------+------------+----------+-------+-------+---------+----------|
| | g35 v | | 1.101 | | 0.917 | -7.160 |
| U9357 | A v -> Y ^ | INVX1 | 3.186 | 5.666 | 6.583 | -1.494 |
| U9293 | A ^ -> Y v | INVX1 | 1.807 | 1.734 | 8.317 | 0.240 |
| U8504 | A v -> Y ^ | INVX1 | 3.386 | 2.575 | 10.892 | 2.814 |
| U8477 | A ^ -> Y v | INVX1 | 1.729 | 1.346 | 12.237 | 4.160 |
| U6039 | A v -> Y ^ | OAI21X1 | 0.709 | 0.726 | 12.964 | 4.886 |
| \DFF_1048/U4 | B ^ -> Y v | MUX2X1 | 0.710 | 0.171 | 13.135 | 5.057 |
| \DFF_1048/U3 | A v -> Y ^ | INVX1 | 0.183 | 0.235 | 13.369 | 5.292 |
| \DFF_1048/Q_reg | D ^ | DFFPOSX1 | 0.183 | 0.000 | 13.369 | 5.292 |
+------------------------------------------------------------------------------+
Clock Rise Edge 0.000
+ Drive Adjustment 0.003
= Beginpoint Arrival Time 0.003
Other End Path:
+------------------------------------------------------------------------------+
| Instance | Arc | Cell | Slew | Delay | Arrival | Required |
| | | | | | Time | Time |
|-----------------+------------+----------+-------+-------+---------+----------|
| | CK ^ | | 0.021 | | 0.003 | 8.081 |
| CK__L1_I0 | A ^ -> Y ^ | CLKBUF2 | 0.043 | 0.086 | 0.089 | 8.167 |
| CK__L2_I1 | A ^ -> Y ^ | CLKBUF3 | 0.058 | 0.124 | 0.213 | 8.290 |
| CK__L3_I6 | A ^ -> Y ^ | CLKBUF2 | 0.040 | 0.094 | 0.307 | 8.384 |
| CK__L4_I16 | A ^ -> Y ^ | CLKBUF3 | 0.039 | 0.116 | 0.424 | 8.501 |
| CK__L5_I48 | A ^ -> Y ^ | CLKBUF1 | 0.047 | 0.071 | 0.495 | 8.572 |
| CK__L6_I239 | A ^ -> Y ^ | CLKBUF1 | 0.069 | 0.087 | 0.581 | 8.659 |
| \DFF_1048/Q_reg | CLK ^ | DFFPOSX1 | 0.069 | 0.001 | 0.582 | 8.660 |
+------------------------------------------------------------------------------+

Here, g35 is the input pin. I am a little bit confused that why the delay of U9357 (only a inverter) can be 5.666 ns. Further, all the setup violations happen on the inclkSrc2reg group. Can somebody tell me how to solve such problem? Thanks very much!

Best,
Dennis