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Need Code for 0 to 1 Transition

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carrot

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Hi ,

When input is transitioning from 0 to 1, output should be asserted for 1 cycle (in same cycle) with synchronous clock.
how will the verilog code look like?

Thanks,
Carrot
 

always@(posedge clk 0r negedge rst)
begin
if(~rst)
a_f <= 1'b0;
else
a_f <= input_a;
end

assign zero_to_one_transition = !a_f && input_a;

always@(posedge clk 0r negedge rst)
begin
if(~rst)
output_f <= 1'b0;
else if(zero_to_one_transition)
output_f <= 1'b1;
else
output_f <= 1'b0;
end

endmodule

Hope this helps
 
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    carrot

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can u clearly explain?? i cant understand your requirement??
 
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    carrot

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Something like this:

Code Verilog - [expand]
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reg your_signal;
reg delayed_your_signal;
reg edge_detect;
 
always@(posedge clk) begin
    delayed_your_signal <= your_signal;
    edge_detect         <= your_signal & ~delayed_you_signal;
end


The "your_signal" can be a module input instead of a register, etc. But you get the idea.

- - - Updated - - -

Oh wait, I read it wrong. You say "in same cycle". Then you want a combinational circuit on the output. In which case sakthikumaran87 already gave you the answer. The "zero_to_one_transition" signal is what you want then. Anyways, if neither of the offered options is what you're looking for, please clarify the requirements.

- - - Updated - - -

Also see this thread on the same topic.
 
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