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[CDR] input data rate and the loop bandwidth

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jihrenee

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It's desirable to maintain a constant ratio between the input data rate and the loop bandwidth of the CDR.
Why? What will happen if there is no constant ration between them?
 

In general, PLL's are 2nd order feedback loops. A zero is introduced so that at crossover, there is sufficient phase margin for stability. Above the loop bandwidth, it is desirable to introduce another pole for noise rejection (primarily, for rejecting the noise introduced by the charge pump, which operates at the clock rate).

IMO, there is no problem with running a clock faster without increasing the loop bandwidth (other than that the loop is slower than it really needs to be). However, decreasing the clock frequency without decreasing the loop bandwidth can have a very noisy result.

Perhaps somebody else who has greater experience with CDRs can offer more insight.
 

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