[SOLVED] smallest no of transistors

is there any formula for designing a cmos logic gate for any given function with smallest no of transistors

I dont think so
There are some method for minimum
number of gate

It is my opinion that the gate has to perform the function to the best of it's capabilty. You want high gain and you want the high voltage associated with logic level. These are the two nuisances that will lead to the design that already exists for the gate.

I think this is related to logic styles. For example, dynamic logic uses less transistors than static CMOS but the former consumes much more power.

However, no explicit formula exists.

nks7 said:

is there any formula for designing a cmos logic gate for any given function with smallest no of transistors

Click to expand...

There is no law.it's the skill of a design to create a gate with the minimum og gate and the least area but still meet the spec

Yes, there is a rule of thumb for minimizing the number of CMOS transistors in a design.

For every inverter required in your design it takes two transistors. A non-inverting buffer capable of full Vdd to Vss swing takes four. For each nand or nor gate it takes 2*n transistors for every input to the gate you are designing. For example, a two input NAND takes 4 transistors, a three input NOR takes six, and eight input NAND takes 16 and so on.

golfbumb said:

Yes, there is a rule of thumb for minimizing the number of CMOS transistors in a design.

For every inverter required in your design it takes two transistors. A non-inverting buffer capable of full Vdd to Vss swing takes four. For each nand or nor gate it takes 2*n transistors for every input to the gate you are designing. For example, a two input NAND takes 4 transistors, a three input NOR takes six, and eight input NAND takes 16 and so on.

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That's a rule of thumb. It's just the implementation. Can you tell me the rule of thumb how many transistors require for a Xor, Xnor, a Flip flop or a transfer gate?

I know a CMOS Xor/Xnor gate can be implemented with 10 transistors, but I don't know whether or not this is the lower limit for the number of transistors.

Actually this kind of problem is more already solved. It is matter of combination.

There are always trade-off between area ( number of transistors) and strenght of output signal and delay time. So no rule of thumb !

What software you guys use for IC design? Cadence IC ?

To "gerryhsu":

We are discussing the smallest number of transistors as the original post asks. It does not talk about area, strength of output, delay, or any other criteria. So, unless you demonstrate otherwise, YES, there still is a "rule of thumb." If you can demonstrate the examples I gave with fewer FETs then the rule of thumb can be reduced.

To "djalli":

Kindly tell us what is the meaning of "Actually this kind of problem is more already solved. It is a matter of combination." Is the solution in another post? Is it obvious to the casual observer? A combination of what?

To "Hughes":

You are correct, the "basic" Xnor and Xor minimum is 10 gates. However, the "Wang" 2 input Xor gate functions with six FETs. See the section labelled "8.3.3.1. Preprocessing Stage" of **broken link removed** for a schematic.

To "dumeHCM:"

See the above paragraph for Xor and Xnor. A practical rail to rail transfer gate (non-inverting buffer) takes four FETs. A two transistor [degraded] transfer gate can be made by transposing the PMOS and NMOS device in a standard inverter. But the source and sink voltages are significantly restricted by doing so. A generic "flip-flop" minimum is dependent on the device, e.g., D, JK, RS ...

Yes, there is a six transistor Xor gate.
I guess what djalli was suggesting is that
"More" (the name of the guy) has already solved
the problem which is the minimal gate realisation
criterio of a given boolean function. Now again
I dont think that there is formula that will guarantee
minimum number of transistor. This is related to
the way you synthesize the logic function. You can minimize the number of gate though and there is certainly a link between that and the number of
transistor, but number of transistor depends on how
you implement the actual gate.
Once you synthesized, you can estimate the number of transistor.
If your constraint is minimum number of transistor,
you have to synthesize for two constraint
1. Minimum number of gate
2. These gate should have minimum number of
transistor.
I know that More addresed the first problem, but
I never heard a problem that is guaranteeing
both of them.

golfbumb said:

To "gerryhsu":
To "djalli":

A combination of what?

Click to expand...

Combination of transistors. Called sometimes optimization.

who care for the smallest number of transistor. The optimization of the performance is the key point for IC design

pass transistor logic may be the best way to reduce the number of transistor,but i think it is difficult,especially in complex logic

yes, pass transistor logic require less transitors

There is no formula ..but we use eulers method in CMOS logic design..