kingslayer
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Dear all,
I am sorry with advanced members, since for most of you this is probably a naive question
I am using Encounter Digital Implementation System 10.12 from Cadence, for RTL-to-GDSII backend flow of a simple modified MIPS processor; I synthesized the Verilog design using RTL Compiler against 45nm NanGate standard-cell library. I already performed placement and routing and I have GDSII output file.
Now, I need a very simple information, but I cannot get the most flexible way to do this (I want to do this by scripting). I would like to know the dimension and the physical placement coordinates of selected modules from the top-level RTL design. For instance, assume that from the top-level design "core" I am interested in "exec_stage" and "mem_ctrl": how can I get the physical dimension (in terms of height and width) of the envelope in which logic is placed for both modules? How can I get the (x,y) starting coordinate (bottom y, leftmost x)?
Thanks in advance for your help
Cheers
scorbetta
I am sorry with advanced members, since for most of you this is probably a naive question
I am using Encounter Digital Implementation System 10.12 from Cadence, for RTL-to-GDSII backend flow of a simple modified MIPS processor; I synthesized the Verilog design using RTL Compiler against 45nm NanGate standard-cell library. I already performed placement and routing and I have GDSII output file.
Now, I need a very simple information, but I cannot get the most flexible way to do this (I want to do this by scripting). I would like to know the dimension and the physical placement coordinates of selected modules from the top-level RTL design. For instance, assume that from the top-level design "core" I am interested in "exec_stage" and "mem_ctrl": how can I get the physical dimension (in terms of height and width) of the envelope in which logic is placed for both modules? How can I get the (x,y) starting coordinate (bottom y, leftmost x)?
Thanks in advance for your help
Cheers
scorbetta
