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Verilog synchronous assign vs combinatorial assign

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shaiko

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Some Verilog questions :

1. Is "wire" used only for combinatorial logic and "reg" only for synchronous ?
2. The "assign" keyword together with the = operator is used only for "wire" while the <= operator is used only for "reg". correct ?
 

For an answer in correct Verilog terms, you should preferably refer to a text book or Verilog specifications.

The answer to both questions is "no".

The basic difference is between continuous assignments driving nets ("wire") and procedural assignments driving variables, e.g. reg, real and integer.

Procedural assignments can be both combinatorial and edge sensitive (synchronous) and use blocking "=" or non-blocking "<=" assignment operators.
 
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    shaiko

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when you say "procedural assignments" you mean assignments under "always" ?
 

See IEEE Std 1364:
6.2 Procedural assignments
Procedural assignments occur within procedures such as always, initial, task, and function.
Click to expand...
 

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