clock signal being the select of a mux

what are the problems if clock signal is used as the select signal of a mux?
is their any problem with this approach

Very simple.

There is no problem in using the clock signal as select input for multiplexer.

Mux operation depends on the clock value at that instant of time. This is also known as Time Division Multiplexing. (TDM)
eg: Consider a 2to1 Mux. When clock signal (Select S) is '0' the the first input(a) comes out of the MUX and when it goes to '1' the second input(b) comes out of the MUX. You can have the time division as you like i.e having clock input '0' for t1 sec and '1' for t2 sec. t1 and t2 can be of your wish.

All the best.

im afraid that linting tool and synthesis tool complains about this...
can tht be ignored?

Prashanth.vinnakota said:

Very simple.

There is no problem in using the clock signal as select input for multiplexer.

Mux operation depends on the clock value at that instant of time. This is also known as Time Division Multiplexing. (TDM)
eg: Consider a 2to1 Mux. When clock signal (Select S) is '0' the the first input(a) comes out of the MUX and when it goes to '1' the second input(b) comes out of the MUX. You can have the time division as you like i.e having clock input '0' for t1 sec and '1' for t2 sec. t1 and t2 can be of your wish.

All the best.

Click to expand...

I dont know about those complaints by those tools. But it is no wrong in doing such design. In fact its existing one.

Hi,

There will definitely be a problem, if you are using a continuously switching signal as a select.

You need to have a clock gating check performed at these points, and if you are getting a violation then you need to fix them before proceeding.
The clock gating check can be ignored only in the case when the select signal of the mux is static during the operation, else there would be undue clipping of the signal.

Is the warning related to this or someting else ?
Please do not proceed on theretical concepts only, go through all warnings and errors...


thanks,
Shobhit

hi shobit,
the clock signal is used as the select of a mux for selecting 2 data input signals to the mux..
when it is 0...input 1 is selected ...when it is 1 input 0 is selected
if the inputs of the mux were clocks rather than data...clock gating checks are to be done as u said...
but in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?
This select clock is always toggling...
please explain ...

shobhit said:

Hi,

There will definitely be a problem, if you are using a continuously switching signal as a select.

You need to have a clock gating check performed at these points, and if you are getting a violation then you need to fix them before proceeding.
The clock gating check can be ignored only in the case when the select signal of the mux is static during the operation, else there would be undue clipping of the signal.

Is the warning related to this or someting else ?
Please do not proceed on theretical concepts only, go through all warnings and errors...


thanks,
Shobhit

Click to expand...

Can you post the exact warning ?

hi shobit,
this design is still in architectural phase...
we need to actually account for all possiblities into consideration..
thswhy......
Please explain the problem that u have experienced as well as the solution to overcome the same...

shobhit said:

Can you post the exact warning ?

Click to expand...

- - - Updated - - -

rahter than clock gating ....have u seen any problem with this approach...

shobhit said:

Can you post the exact warning ?

Click to expand...

- - - Updated - - -

rather than clock gating have u experienced any other problem with this approach..?

shobhit said:

Can you post the exact warning ?

Click to expand...

in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?

Click to expand...

The question can't be answered without considering the purpose of the mux output signal. Instead of raising general questions, you should analyze your design's timing. in detail.
A mux driven by a clock can be e.g. found in DDR output buffers, but it's of little use for internal logic, I think.

FvM said:

The question can't be answered without considering the purpose of the mux output signal. Instead of raising general questions, you should analyze your design's timing. in detail.
A mux driven by a clock can be e.g. found in DDR output buffers, but it's of little use for internal logic, I think.

Click to expand...

Yes. Its a valid design. Needed some clarity on errors faced.

- - - Updated - - -

dll_fpga said:

hi shobit,
the clock signal is used as the select of a mux for selecting 2 data input signals to the mux..
when it is 0...input 1 is selected ...when it is 1 input 0 is selected
if the inputs of the mux were clocks rather than data...clock gating checks are to be done as u said...
but in my case the clock signal is used for selecting data inputs...
So is it necessary to fix the clock gating violations?
This select clock is always toggling...
please explain ...

Click to expand...

Hi dll,

Your question on design was already answered. Kindly quote the errors reported in detail.

You may run into issues if clk appears in the combinatorial path for a register that is clocked off of clk or a derived version. In such cases, the input to the FF will change near the same time as the FF's clock signal.

You may run into issues if clk appears in the combinatorial path for a register that is clocked off of clk or a derived version. In such cases, the input to the FF will change near the same time as the FF's clock signal.

Click to expand...

Yes, but this scenario doesn't seem to serve a reasonable purpose.

STA become critical

dftrtl said:

STA become critical

Click to expand...

can u provide some details/explanation/links on this?

When I use the term "clock" I am referring to a signal that can drive the clock input of a flip-flop. A clock can be internally generated or ported in through a pad but in either case you must first pass that signal through a test mux that can switch the clock source when running atpg_tests. In mission mode the input and output of this mux will be the same but you CANNOT connect the input signal to the clock input of a flip-flop, you must run it through the mux or you won't be able to run atpg tests.

So no you cannot connect a "clock" to the select input of a mux for the simple reason that it is not the clock input of a flip-flip. You can connect the pre-dft mux version of that clock and it will work. That signal will be identical to the clock but can be used in logic cones that terminate at a D input of a flip-flop without harming the atpg testability.The errors that you are seeing are atpg testability errors.