matrix39
Newbie level 4
hi dear
i want to interface Micron's SDRAM MT48LC4M32B2 with the spartan-6 and want to use the built in memory controller.
i am confused about how should DQM0-DQM3 pins be connected to FPGA...in DDR or DDR2 there are LDQS, UDQS nd LDM,UDM pins.
can i avail this MCB feature of spartan-6 moreover this SDRAM is being powered by 3.3V ??
can i use MIG for its interface design because it does not list SDRAM ??
Which I/O standard is good for my scenario if single ended interface is planned ??
IS there a free ip core available in ISE/EDK or on any other site??
Can i safely place SDRAM and DDR2 on the same board and stuff only one as per need and share the signals b/w them ??
best regards
matrix
i want to interface Micron's SDRAM MT48LC4M32B2 with the spartan-6 and want to use the built in memory controller.
i am confused about how should DQM0-DQM3 pins be connected to FPGA...in DDR or DDR2 there are LDQS, UDQS nd LDM,UDM pins.
can i avail this MCB feature of spartan-6 moreover this SDRAM is being powered by 3.3V ??
can i use MIG for its interface design because it does not list SDRAM ??
Which I/O standard is good for my scenario if single ended interface is planned ??
IS there a free ip core available in ISE/EDK or on any other site??
Can i safely place SDRAM and DDR2 on the same board and stuff only one as per need and share the signals b/w them ??
best regards
matrix