FPGA input buffer current consumption

I have an FPGA Bank whose all pins are solely defined as inputs.
The Tx side of these pins (a DSP IC) isn't always active - sometimes it's switched off...

When the Tx side is switched off - I see rise in the current consumption of the specific bank (a few hundred microamps).
As soon as the Tx side (the DSP) is switched on the current drops almost to zero.

How can this phenomenon be explained ?
Is it possible that the current consumption is caused due to noise induced switching of the input buffers ?

If "switched off" means tri-stated, you can expect a rise of buffer current consumption when the input voltage floats to intermediate values. It's the same with any CMOS buffer.

A hold circuit can be used to prevent input floating, at the expense of slightly increased dynamic power dissipation.

Is it because of noise induced false switching ?

Noise may play a role, but static current consumption of a CMOS buffer with intermediate input voltage is sufficient to explain the effect.

by "intermediate input voltage" - do you mean the undefined level between logic "High" and "Low" ?

Yes, not necessarily undefined, but outside defined low or high levels. There are in fact two possible sources of additional buffer currents:
- static currents due to simultaneous conduction of P and N Fets in a CMOS inverter or gate. It should be noticed, that asymmetric CMOS structures, e.g. in 74HCT or some Multi-IO-voltage FPGA input buffers can also involve static currents with "legal" logic levels.
- dynamic currents caused by transistor capacitances during switching. "Noise" at floating inputs will also cause dynamic currents.

Can you describe the "bus keeper" circuit you mentioned ?
Did you mean a simple weak pull resistor parallel to the Rx end ?

As FvM mentioned, many FPGAs/CPLDs have an optional 'bus keeper' circuit built into each I/O pin's internal interface circuit.

When enabled on a pin, a small internal buffer with limited output current drives a high onto that pin when its above the logic high threshold and a low onto that pin otherwise. This is to try and keep that pin at the last logic level it held before being tri-stated etc.

This keeper current can be quite strong. On some devices, it can get as high as the same strength as a 5K pull-up/pull-down resistor. Check that your connected circuitry is happy with this. Driving logic gates usually overcome it with ease but weaker circuits may not. Just something to be aware of

I've also configured pins as LVTTL instead of LVCMOS to help avoid your over-currenting, as (LV)TTL has a narrower 'unknown' input voltage range than CMOS.

Bus keeper or bus hold circuits provide positive feedback to the input pin through an output stage of limited current capability. It's described in many FPGA datasheets, e.g. from Altera. I agree with tony that you should check the drive strength of the connected output if it's able to drive the bus hold circuit. Regular logic families and other digital push-pull outputs can do.

I've also configured pins as LVTTL instead of LVCMOS to help avoid your over-currenting, as (LV)TTL has a narrower 'unknown' input voltage range than CMOS.

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It's questionable if changing the IO standard within the same IO voltage actually changes input thresholds. I know that a number of FPGA families don't. The regular single ended IO standards are mainly a rule to map nominal drive strengths to output transistor configurations, but don't econfigure input stages. But may be some FPGA families have the feature.

FvM said:

It's questionable if changing the IO standard within the same IO voltage actually changes input thresholds. I know that a number of FPGA families don't. The regular single ended IO standards are mainly a rule to map nominal drive strengths to output transistor configurations, but don't reconfigure input stages. But may be some FPGA families have the feature.

Click to expand...

Yes, I'd agree with that (I cautiously placed my 'also' and 'help avoid'!). I'm fairly confident LVTTL/LVCMOS do change the input thresholds but aren't pushing the point as it won't solve the problem - I'm saying I use the LVTTL setting as free belt and braces

The real thing is that a bus keeper or internal/external pulling resistors are what will solve the problem.