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Power compiler for power gating technique

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anuradha.verma

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Hello,

How to invoke power compiler from design compiler gui design vision.
Is it possible to insert power gating technique using power compiler.


Thanks
 

Power compiler is inbuilt in DC if you buy the latest version of DC. It Depends on the agreement with synopsys. only way to check is, try simple Power compiler commands in DC shell or read the top 10 lines while invoking the tool, which tell Power compiler is read with DC or not.

Typical flow to insert Power gating is as shown below:

1. DC will synthesize the design and convert to gate level netlist
2. Formality performs the FV between RTL+UPF Vs Netlist + UPF
3. MVRC and MVSIM performs the static rule checks and simulation including the power states, shutdown and etc.
4. ICC inserts and places the power gating cells and create the Power network.
5. Formality need to verify the DC netlist +UPF vs ICC netlist + UPF
6 . PTPX analyzes the dynamic and static power.

PS : Never used the Power compiler for Power gating insertion.

Regards,
Sam
 
PowerCompiler (or DesignCompiler, as PC does not have own interface) may insert isolators, level shifters, always-on buffers, retention registers during synthesis.

power gating cells are inserted after synthesis by PnR tool (like Synopsys IC Compiler).
 
sam536 said:
Power compiler is inbuilt in DC if you buy the latest version of DC. It Depends on the agreement with synopsys. only way to check is, try simple Power compiler commands in DC shell or read the top 10 lines while invoking the tool, which tell Power compiler is read with DC or not.

Typical flow to insert Power gating is as shown below:

1. DC will synthesize the design and convert to gate level netlist
2. Formality performs the FV between RTL+UPF Vs Netlist + UPF
3. MVRC and MVSIM performs the static rule checks and simulation including the power states, shutdown and etc.
4. ICC inserts and places the power gating cells and create the Power network.
5. Formality need to verify the DC netlist +UPF vs ICC netlist + UPF
6 . PTPX analyzes the dynamic and static power.

PS : Never used the Power compiler for Power gating insertion.

Regards,
Sam
Click to expand...

Hi

thanks for the flow.
i gone through the first 10 lines while tool is being invovked.it says power compiler is read with DC.
 

Why Power Gating cells should be inserted by P&R tools, but the isolators, level shifters, always-on buffers, and retention registers by a FronEnd synthesis tool?
Does the isolators, level shifters, always-on buffers, and retention registers not require the placement information, but the Power Gating cells do require? Why?
 

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