Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

placement finish with setup violations

Status
Not open for further replies.

ee1

Full Member level 2
Joined
May 31, 2011
Messages
120
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
2,036
Hi,
When i finish placement i see some setup violations.
I have worst negative slack of 0.6 ns.
my question is:
some of the other violations are ~ 0.5 ns , and i can see some long delays (~ 0.6-0.8 ns) in some of the path stages.
but, icc didn't size the buffer, althought he could.
why does this happend?
is it because the tool put all its effort in the WNS?

how can I fix it?

Thanks!
 

Hi,
When i finish placement i see some setup violations.
I have worst negative slack of 0.6 ns.
my question is:
some of the other violations are ~ 0.5 ns , and i can see some long delays (~ 0.6-0.8 ns) in some of the path stages.
but, icc didn't size the buffer, althought he could.
why does this happend?
is it because the tool put all its effort in the WNS?

how can I fix it?

Thanks!

hi.....

I dont knw whether u have used setAnalysisMode -checkType setup..If u want to fix hold use optDesign -preCTS -hold...If u use this command, it will fix only hold by buffering ,cloning and Resizing..It wont check Setup violation....If u want to fix setup use
optDesign -preCTS alone........ I hope this may help u..
 

This can be due to high standard cell density in that particular area where buffer is placed.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top