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[SOLVED] Region of operation of cascodes in a current mirror

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DharmaSlice

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Hi,

In a cascode current mirror Im using NMOS devices to take in the input current and mirror it up to PMOS devices.

Under low temperature condition the cascodes above the NMOS transistors go into region 3. Is this ok ? And whats the full explanation of region 3 ?

Thanks
 

Dear DharmaSlice
Hi
Can you show us the literature that you are referring to , please ?
Best Wishes
Goldsmith
 

Hi,

Its from my simulator. I have found its referring to SUB THRESHOLD region.

So my Vgs < Vt

So I guess I need to increase my gate voltage to pull it back into the Saturation region.
 

If Vgs is lower than VT your mosfet is turn off ! but if you put 15 volts across the GS junction it will be on . are you referring to these things ?
 

To the simulator, as long as vdsat=Vgs-Vth<0, they will flag the MOS as operating in region 3, and defines it as the sub-threshold region. It's stupid.
In reality, the region of vdsat<0 actually comprises of the week inversion region (sub-threshold), and part of the moderate inversion region.

In the weak inversion region, the I-V is exponential.
In the strong inversion region, the I-V follows the square law.
In the moderate inversion region serves as the transition region between the 2 above.

I'll bet you have very large aspect ratios for the cascode, which can push it into moderate inversion, to the extent of negative vdsat.
However, the cascode still works. It's normal. What you have to check is if the moderate inversion region is well-modeled by your model files. Otherwise what you simulate may not correlate with the actual silicon.
 
To the simulator, as long as vdsat=Vgs-Vth<0, they will flag the MOS as operating in region 3, and defines it as the sub-threshold region. It's stupid.

Hi checkmate,

didn't you think of veff=Vgs-Vth<0 ? I think vdsat > 0 (always). At least to the definitions I'm familiar with.

E.g. see the figure in this posting.
 

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