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Problem with TSPC flipflop simulations

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viperpaki007

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Hi,

Can any body explain how the positive and negative edge triggered flip-flop works in the following link

**broken link removed**

I have made the same flip flop (as divider) in cadence in 130nm process for high speed operation but the simulation results show a voltage glitch at the output. I don't know what is the reason for that. Screen shots of results are attached.

Clock frequency 2GHz
Rise time 25ps
Fall time 25ps
Supply voltage 1.2V

 

I found the problem by myself. The flipflop was not loaded properly. I increased the loading to 100fF in order to make it more practical and the circuit does not have any glitches anymore
 

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