arm946es STA script--sharing with you!

write_sdf, primetime

#----------------------------------------------------------------------------

# Set option values

set verbose 0 ;# 1 for verbose source commands

set noscan 1 ;# False path the SCANEN input
set signoff 0 ;# Use post layout netlist and parasitics
set spef 1 ;# Use spef or dspf format parasitics

set clk_period 8.00 ;# Target clock period in ns
set io_clk_period 8.00 ;# Target I/O clock period in ns
set clk_uncertainty 0.20 ;# Expected clock skew in ns
set min_latency 0 ;# Minimum clock latency under WCS
set max_latency 0 ;# Maximum clock latency under WCS

# ----------------------------------------------------------------------------------
# Set up technology for PrimeTime
# ----------------------------------------------------------------------------------

if { $verbose } {
source -echo -verbose ./scripts/tsmc18.tcl
} else {
source ./scripts/tsmc18.tcl
}

# Read in the Verilog netlist for the design
if { $signoff} {
set svr_keep_unconnected_nets true
read_verilog ./layout/ARM946ES.v
} else {
read_verilog ./db/ARM946ES.v
}

# Link the design hierarchy
current_design ARM946ES
link

# Create and define clocks
if { $signoff } {
create_clock -period $clk_period CLK
set_propagated_clock CLK
create_clock -period $clk_period UnGatedCLK
set_propagated_clock UnGatedCLK
} else {
create_clock -period $clk_period CLK
set_clock_uncertainty -setup $clk_uncertainty CLK
set_clock_uncertainty -hold $clk_uncertainty CLK
set_clock_transition 0 CLK
set clock_name CLK

create_clock -period $clk_period UnGatedCLK
set_clock_uncertainty -setup $clk_uncertainty UnGatedCLK
set_clock_uncertainty -hold $clk_uncertainty UnGatedCLK
set_clock_transition 0 UnGatedCLK
}

# Define context for the design.
set_load $load_value [list [all_outputs]]
set_driving_cell -cell $driving_cell_name -pin $driving_cell_pin [list [all_inputs] ]

set_operating_conditions -min fast -max slow

if {$signoff} {
if { $spef } {
read_parasitics -complete_with wlm ./layout/ARM946ES.spef
} else {
read_parasitics -complete_with wlm ./layout/ARM946ES.dspf
}
}

if { $verbose } {
source -echo -verbose ./scripts/arm946es_constraints.tcl
} else {
source ./scripts/arm946es_constraints.tcl
}

update_timing

redirect ./pt/ARM946ES.report { check_timing -verbose }

if { $noscan } {
set_false_path -from SCANEN
}

redirect -append ./pt/ARM946ES.report { report_design }
redirect -append ./pt/ARM946ES.report { report_clock }
redirect -append ./pt/ARM946ES.report { report_exceptions }
redirect -append ./pt/ARM946ES.report { report_port -verbose }
redirect -append ./pt/ARM946ES.report { report_analysis_coverage }
redirect -append ./pt/ARM946ES.report { report_bottleneck }
redirect -append ./pt/ARM946ES.report { report_wire_load }

redirect ./pt/ARM946ES.input-max-timing { report_timing -delay_type max -max_paths 500 -from [all_inputs]}
redirect ./pt/ARM946ES.input-min-timing { report_timing -delay_type min -max_paths 500 -from [all_inputs]}
redirect ./pt/ARM946ES.output-max-timing { report_timing -delay_type max -max_paths 500 -to [all_outputs]}
redirect ./pt/ARM946ES.output-min-timing { report_timing -delay_type min -max_paths 500 -to [all_outputs]}
redirect ./pt/ARM946ES.violators { report_constraint -all_violators }

set_false_path -from [all_inputs]
set_false_path -to [all_outputs]

update_timing

redirect -append ./pt/ARM946ES.reg2reg-max-timing { report_timing -delay_type max -max_paths 500 }
redirect -append ./pt/ARM946ES.reg2reg-min-timing { report_timing -delay_type min -max_paths 500 }

# Dump these for PC post layout opt.
write_script -output ./pt/ARM946ES.setload
write_sdf -version 2.1 -context verilog ./pt/ARM946ES.sdf

quit