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standby current in CMOS circuits

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seamoss

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Hi,

I wanted to know why would a floating node/gate have standby current concern? I know that people would leave a lot of spare gates in their circuits, but is there a concern for standby current if a lot of spares are used?

Thanks!
 

The answer is simple. You must not leave spare gate inputs floating. They need to be tied to GND or VDD.

When you set the input of a CMOS inverter e.g. to VDD/2, both transistors are turned on, causing a transverse or "shoot-through" current.
 
Normally the two complementary transistors in a basic CMOS inverter gate are in a one or zero state where one transistor is ON and the other is OFF. Thus the only current drawn is the leakage current through the OFF transistor, which is very small. However if the input gates are allowed to float, they may go to an intermediate voltage that allows both transistors to be partially on at the same time. This greatly increases the current through the gate. In some cases it can actually cause the gate to burn out. Thus you always tie any unused CMOS inputs to either a logic zero or a logic one.
 
Got it, thanks. So basically the gate of any transistor inside the circuit should not be floating. We can float the drain/source but gate should go to one of the rails.
 

It is a common problem when designing low-power CMOS circuits, to accidentally leave a gate floating [esp. in shutdown mode. I've had this problem :sad: ]. If you have a very large circuit, it can be hard to catch this problem, too (your simulator often won't indicate it's floating). Then after you have your chip fab'd, your test engineer comes back to you and asks why your chip is taking 1mA standby current instead of 1uA... it's a sobering moment.

Some people write plug-ins for their simulators which find floating nodes, by applying a tiny upwards or downwards current to every node in the circuit. If the state of anything changes, then you know you have a floating node.
 

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