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[SOLVED] Behavioral Verilog code to suppress even pulses of clock signal

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venugopala_0202

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Hello

Recently I attended an interview. The following was one of the questions that were asked-

A module has two inputs, clk and reset. Write a verilog code to suppress the even pulses of the clock.

Could someone here post a verilog code to do this?
 

This is frequency divide by 2 question without 50% duty cycle. One way to do is

Code: 
module divby2(
              input clk,
              input reset,
              output div_clk);

reg  div_clk_q;
wire div_clk_d;

always @ ( posedge clk, negedge reset) begin: clk process
     if(!reset) begin
           div_clk_q <= 1'b0;
     end else begin
           div_clk_q <= div_clk_d;
     end
end

assign div_clk_d = ~div_clk_q;
assign div_clk   = div_clk_q & clk;

endmodule

Assumption, active low reset.
 
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