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Role of Verification Engineer ?

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raki31

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Hi All,

Can any one please explain me roughly, what the VLSI front end Verification engineer role and thing he will be doing ?

Thanks in Advance.

@ raki
 

VLSI front end refers to Design Field. RTL Design, VHDL/Verilog designs, FPGA/ASIC Designs etc.

Verification is Post Simulation task. Usually its a back end step.

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All the tasks between front end design(till simulation step) and actual chip fabrication are collectively quoted as back end design(functional and timing Verification tasks followed by physical Verification) in VLSI.
 

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