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why make the resistance pmos network and nmos network equal

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owen_li

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Hi.
I am a digital backend engineer, and have no much understanding about CMOS transistor.
I read a book these days and found it said "the resistance of pMos network should equate that of nMos network, in CMOS transistor".
like a inverter, the pMos should be nearly two times width than nMos, to make their resistance equal.
So, Can you tell me why ?

Thanks in advance!
 

Thanks FvM.
So, can you tell me why we should make the rise time and fall time equal, when designing gates ?
 

owen_li said:
Thanks FvM.
So, can you tell me why we should make the rise time and fall time equal, when designing gates ?
Click to expand...
So the the time delay through the gates is essentially the same for both rising and falling edges. It simplifies the timing calculations when determining the maximum frequency that the circuit can operate and if there are any race conditions.
 

Thanks crutschow.
Actually, even though the resistance of the pMos network equate the resistor of nMos network, the rise and fall time will be different from each other.
coz the rise and fall time depends on another factor: capacitance.
So, what is your solution when you draw the transistor ?
Do you both consider resistance and capacitance impact ? or Just consider the equal resistance for pMos and nMos network ?

Thanks very much!
 

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