LDO VCCS compensation

Hi！Did anyone done LDO VCCS compensation? I did a LDO VCCS compensation, through the voltage-controlled current source to introduce a zero point to elimanate the second main pole. but I have a question, is this VCCS output between access R1,R2 will affect the static working point? as shown in Figure 1 NETF points on a current path,


Figure 1

Figure 2
This can provide exchange of small signal current, but there is some static circuit outflow or inflow, affect the output precision LDO, I do not know how to fix it, I feel hard for in the VCCS control circuit to reduce the affect to the Vout, if current mirror and current sources of pipes in Figure 3 are 1:5, is part of the static current branch flowing into R1, R2.

Figure 3
Then I think about VCCS is compensation capacitor of evolution and compensation capacitors are not production or absorption of quiescent current, however voltage-controlled current source may produce static electricity. And the bias current is random, deviation of temperature change as technology changes may make great effect on Vout (when T drift, PSR is bad). I have not classmate who did this LDO compensation around, so I don’t know what to do. Hope someone can help me about the experience.
with my great appreciation.

To me this looks simply like "feedforward compensation" in
the feedback ladder. You see it often enough in regulators.
Also called "Type III" compensation. There should be no DC
term, then your concerns about temperature drift (from that)
go away. PSRR should be improved at medium frequencies
where you are making better use of amplifier loop gain, and
still have some. DC PSRR would be unaffected (no DC term)
and HF is really on the output filter (though amplifier design
can maximize it somewhat, your PMOS pass device is just
itching to amplify any supply noise).

Thank you.So you mean that I shouldn't concern DC term ,and I should focus on Tran term? But now tran voltage is not what I want because some DC current of VCCS flow into R1 then the current flowed R2 is smaller than I wish so that (i2*R2+i1*R1) is smaller than regulator.Shoud I change the W/L of the VCCS to make the DC out current be zero? Is that reliable?