How to interface NIs ADC081000 (1Ghz) to a FPGA(200Mhz)?

ad &fpga

how can i interface NI's adc081000 (1Ghz) to a FPGA(200Mhz)? thanks

ad &fpga

In theory, it's ok but remember that it will loss your performance of the ADC. Just up to you !

Re: ad &fpga

Dear asmer,
If you have to stay with your FPGA and have no other alternative, then you need to start thinking about a way to slow down the flow of data.

One quick idea, it to find a high speed FIFO, with 1GHz, it will be really difficult, but if you find a FIFO that has the possibility to change the data width of the information. According to the datasheet for the component, the output of the ADC is 16 bits LVDS at max 500 MHz. By putting a 16/32 FIFO between the ADC and your FPGA, your datarate will go down to 250 MHz. It maybe OK for your FPGA to handle, but I would really look for something else if I was you.

Todays FPGAs can handle up to 650MHz datarate, I would deffinitely go for a faster FPGA, then you connect the FPGA pins to the output of the ADC directly, it will be a much cleaner design with the minimum amount of components on that board.

There are other way to slve this, depending on what you want to do with the captured data, 1G Bytes of information is a hell of a lot and you need a really big FPGA or a gigantic memory of you want to do any signal processing on it. And big FPGAs today, can handle really high speed LVDS signals and 500MHz data rate will not be a big problem for them.

Good luck with your design,

/Farhad

Re: ad &fpga

asmer said:

how can i interface NI's adc081000 (1Ghz) to a FPGA(200Mhz)? thanks

Click to expand...

You can use a highspeed demux, Atmel makes one that will take 10bits LVDS at 1GHz in 1:8 mode, or 2GHz input in 1:4 mode. That will get your input freq to the FPGA down to 125Mhz or 250MHz...

Re: ad &fpga

Hi Asmer,
May I ask what FPGA you are using? I am just curious about it.

BR,
/Farhad

Re: ad &fpga

i design with Xilinx's VirtexE 200

Re: ad &fpga

Dear Asmer,
I think you can easily connect your ADC to your Virtex-E device. If you are designing a new PCB, then with good layout work, you can connect the output of the ADC to our FPGA and internally use a 1:2 or 1:4 to lower the data flow to 250 or 125MHz.

You can do that in 2 steps, the first step is to create a demux, as close to the pin as possible, and then send that data to a CLB based FIFO created by the coregen and it will create a 64bits @ 125MHz that is pretty easy to handle inside the V200E device. One additional help is to add a register immediately after the FIFO to make the P&R program a change to handle the data flow easier.

One good example on how to use internal memory of Virtex devices in Data-Width converion is this applications note:

https://www.xilinx.com/bvdocs/appnotes/xapp205.pdf
And this one "170MHz Synchronous and Asynchronous FIFOs Using the Virtex Block SelectRAM+ Features"
https://www.xilinx.com/bvdocs/appnotes/xapp131.pdf


BR,
/Farhad

Re: ad &fpga

Hello!
I have the same task: 8 bit 1Ghz ADC + FPGA. I'm going to use demux. But I need in REAL TIME DSP functions. Is it possible to realise math functions <,>,+,*, and FIR working with 64bit samples, as if it is 8 bit samples?
Many thanks!

ad &fpga

Hi Vacuum, (hehe that's funny)

The Xilinx Virtex-4 and Virtex-5 can input 1 gigabit/sec per differential input, so you may be able to connect your ADC directly to the FPGA. Inside the FPGA, you could split the data into several parallel paths, and process them at a comfortable clock rate.

Why would you want to use 64-bit math if your data is only 8-bit?

Re: ad &fpga

Thank you for reply, echo47!
I know, that Virtex-4 and Virtex-5 like StratixII, StratixIII can input > 1 gigabit/sec, but they are rather expensive. In my plans use low costs Cyclone/Spartan FPGAs with 840Mbps LVDS inputs, so I use 1:2 demux.

It's a good idea of splitting data into several parallel paths, and process them at a comfortable clock rate, as you wrote. But I have confronted with a problem, how to realise this(e.g. how to filter or compare data distributed in different path in real time with immediate result?). Please, recommend me any literature, examples or reference designs about it, if know

ad &fpga

You probably should design your signal processing algorithm using only modules that are easily implemented with parallel processing. For example, a FIR filter uses a sum-of-products that is relatively easy to split into parallel sections. However, an IIR filter is recursive and could be trouble. I haven't seen any great books on this subject. Maybe you can find some inspiration here:
"DSP: Designing for Optimal Results"
**broken link removed**

Do you plan to output 1 gigabyte/sec from the FPGA, or will it be doing some sort of bandwidth reduction?

I don't know your application, but just in case your ADC input is narrow-bandwidth .... Don't overkill by sampling a narrow-bandwidth signal at HighestFrequency*2. A sample rate of bandwidth*2 is sufficient. (Well, maybe a little faster than *2, of course.)

Re: ad &fpga

Fmax in my project <=500Mhz and I'm going to use 1Ghz DAC in output.

ad &fpga

Hopefully your DSP algorithm isn't very complex. In a Spartan-* or Cyclone-* FPGA, multiply-accumulate operations run about 150 MHz to 250 MHz. To achieve 1 GHz data rate, the parallel processing will consume FPGA resources quickly.

ad &fpga

Xilinx's VirtexII spatanII