# rc4 algorithm verilog code

1. ## rc4 algorithm verilog code

pls pls anybody correct my code of RC4 algorithm::

input clk;
input rst;
output reg [7:0] k;
wire clk, rst; // clock, reset

/* RC4 PRGA */
reg [7:0]l;
reg [7:0] key[0:15];
// S array
reg [7:0] S[0:256];

// Key-scheduling state
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4

// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] temp;
reg [7:0] K;

always @ (posedge clk or posedge rst)
begin
if (rst)
begin
i <= 8'h0;
j <= 0;
end
case (KSState)

i <= 8'h00;
KSState <= `KSS_KEYSCHED1;
end

`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
if (i < 256)
begin

S[i] <= i;
i <= i+1;
KSState <= `KSS_KEYSCHED1;
end
else if(i == 256)begin
i <= 8'h00;
j <= 8'h00;
KSState <= `KSS_KEYSCHED2;
end

end
`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
j <= (j + S[i] + key[i % 16]);
KSState <= `KSS_KEYSCHED3;
end
`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
S[i]<=S[j];
S[j]<=S[i];
if (i == 8'hFF)
begin
KSState <= `KSS_CRYPTO;
output_ready <= 1; // Flag keysched finished
i <= 8'h00;
end
else begin
i <= i + 1;
KSState <= `KSS_KEYSCHED2;
end
end

`KSS_CRYPTO: begin // KSS_CRYPTO: Output crypto stream
// It was all nicely pipelined until this point where I don't care anymore
i = i + 1;
j = (j + S[i]);
temp = S[j];
S[j]=S[i];
S[i]=temp;
K = S[ S[i]+S[j] ];
end
default: begin
end
endcase
end

endmodule

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2. ## Re: rc4 algorithm verilog code

please anybody help me to correcting this code.....i need help???

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