- 3rd June 2012, 10:57 #1

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## rc4 algorithm verilog code

pls pls anybody correct my code of RC4 algorithm::

module rc4_i(clk, rst, password_input, output_ready, k);

input clk;

input rst;

input [127:0] password_input;

output output_ready;

output reg [7:0] k;

wire clk, rst; // clock, reset

reg output_ready;

wire [127:0] password_input;

/* RC4 PRGA */

reg [7:0]l;

reg [7:0] key[0:15];

// S array

reg [7:0] S[0:256];

// Key-scheduling state

`define KSS_KEYREAD 4'h0

`define KSS_KEYSCHED1 4'h1

`define KSS_KEYSCHED2 4'h2

`define KSS_KEYSCHED3 4'h3

`define KSS_CRYPTO 4'h4

// Variable names from http://en.wikipedia.org/wiki/RC4

reg [3:0] KSState;

reg [7:0] i; // Counter

reg [7:0] j;

reg [7:0] temp;

reg [7:0] K;

always @ (posedge clk or posedge rst)

begin

if (rst)

begin

i <= 8'h0;

KSState <= `KSS_KEYREAD;

output_ready <= 0;

j <= 0;

end

case (KSState)

`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from password input

key[0] <= password_input[127:120];

key[1] <= password_input[119:112];

key[2] <= password_input[111:104];

key[3] <= password_input[103:96];

key[4] <= password_input[95:88];

key[5] <= password_input[87:80];

key[6] <= password_input[79:72];

key[7] <= password_input[71:64];

key[8] <= password_input[63:56];

key[9] <= password_input[55:48];

key[10] <= password_input[47:40];

key[11] <= password_input[39:32];

key[12] <= password_input[31:24];

key[13] <= password_input[23:16];

key[14] <= password_input[15:8];

key[15] <= password_input[7:0];

i <= 8'h00;

KSState <= `KSS_KEYSCHED1;

$display ("key[%d] = %08X",i,password_input);

end

`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization

if (i < 256)

begin

S[i] <= i;

i <= i+1;

KSState <= `KSS_KEYSCHED1;

end

else if(i == 256)begin

i <= 8'h00;

j <= 8'h00;

KSState <= `KSS_KEYSCHED2;

end

end

`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array

j <= (j + S[i] + key[i % 16]);

KSState <= `KSS_KEYSCHED3;

end

`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation

S[i]<=S[j];

S[j]<=S[i];

if (i == 8'hFF)

begin

KSState <= `KSS_CRYPTO;

output_ready <= 1; // Flag keysched finished

i <= 8'h00;

end

else begin

i <= i + 1;

KSState <= `KSS_KEYSCHED2;

end

end

`KSS_CRYPTO: begin // KSS_CRYPTO: Output crypto stream

// It was all nicely pipelined until this point where I don't care anymore

i = i + 1;

j = (j + S[i]);

temp = S[j];

S[j]=S[i];

S[i]=temp;

K = S[ S[i]+S[j] ];

end

default: begin

end

endcase

end

endmodule

- 3rd June 2012, 10:57

- 17th June 2012, 16:52 #2

- Join Date
- Dec 2011
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- shilong
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## Re: rc4 algorithm verilog code

please anybody help me to correcting this code.....i need help???