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how fpga(spartn6) caputres data in such a interface?

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gauz

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tlk.jpg
Hi all,



In my design there is a TI transcever tlk2211 interfaces to spartn6, which send data(RD) in ddr mode, and sourced with two inverted clk(RBC0/1) to capture the data in each of the rising edge. the waveform as shown in the attachment,



I'm a little puzzled how should I capture the data and sync to the internal clock?

is there any way to merge the two clock to a signle clock and capture the data with this clock?



Thanks,

Gauz
 

I recognize a K28.5 character. This is typically a sync character to help a CDR (clock and Data Recovery) unit retrieve clock and data from this stream of data

You'll need to design a CDR though.
What datarate are you talking about?
 

The TLK has the CDR built-in, so he won't need to design that.

In answer to original question, you don't want to try to merge the clocks, just use them to extract the data according to the data sheet timing diagram. Combine the data after you have received it. The sync/pass pin tells you when the sync charatcer is detected and from that signal you then know the correct order of the data blocks that follow.

Look here for info on the data combining: http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf

Note that he uses both edges of a single clock, you have two clocks using the same edge, so change your code accordingly.
 

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