er.akhilkumar
Full Member level 2
I am trying to write a system verilog property. Actually I am using these properties to write functional coverage. I have signal which goes high on clock negedge. And when I write property for it as following:
A : cover property(@(negedge clock) $rose(signal));
Assertion checks the value at next clock negedge, but I want to check it exact on the rising edge of signal. I am using Cadence NCSIM tool, and when I saw sequence time I realized that this problem is caused by sequence time. Actually after expanding sequence time I saw that signal is going high after some time of the negedge of clock. can anyone please provide solution that how we can remove this delay or is there any property macro by which we can check the signal at its rising time?
Thanx
A : cover property(@(negedge clock) $rose(signal));
Assertion checks the value at next clock negedge, but I want to check it exact on the rising edge of signal. I am using Cadence NCSIM tool, and when I saw sequence time I realized that this problem is caused by sequence time. Actually after expanding sequence time I saw that signal is going high after some time of the negedge of clock. can anyone please provide solution that how we can remove this delay or is there any property macro by which we can check the signal at its rising time?
Thanx
