srawanjoshi
Newbie level 4
Hi all...
I am in a process of designing a low power sram memory array.For that i have designed a single bitline architecture sram cell which consumes less power.Now i have to extend the memory to 256kB (512X512) memory of 4 bit bit word.As a part of this i have to model the bitline and wordline in terms of the wire resistance and wire capacitance. Please suggest me how to model the bitline,wordline etc.....in terms of the wire capacitance and resistance for carryiong out simulations of the entire array.....please suggest some books/manuals/tutorials where i can find the same.....:lol:
I am in a process of designing a low power sram memory array.For that i have designed a single bitline architecture sram cell which consumes less power.Now i have to extend the memory to 256kB (512X512) memory of 4 bit bit word.As a part of this i have to model the bitline and wordline in terms of the wire resistance and wire capacitance. Please suggest me how to model the bitline,wordline etc.....in terms of the wire capacitance and resistance for carryiong out simulations of the entire array.....please suggest some books/manuals/tutorials where i can find the same.....:lol:
